//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
//Date        : Mon Dec  2 09:46:54 2024
//Host        : Laptop-LZY running 64-bit major release  (build 9200)
//Command     : generate_target use_my_ip.bd
//Design      : use_my_ip
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "use_my_ip,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=use_my_ip,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=3,numReposBlks=3,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "use_my_ip.hwdef" *) 
module use_my_ip
   (CLK_10_2024304066,
    CLK_2024304066,
    CLK_20_2040304066,
    CLK_2_2024304066);
  output CLK_10_2024304066;
  input CLK_2024304066;
  output CLK_20_2040304066;
  output CLK_2_2024304066;

  wire CLK_IN_0_1;
  wire fenpinqi_10x_CLK_OUT;
  wire fenpinqi_20x_CLK_OUT;
  wire fenpinqi_2x_CLK_OUT;

  assign CLK_10_2024304066 = fenpinqi_10x_CLK_OUT;
  assign CLK_20_2040304066 = fenpinqi_20x_CLK_OUT;
  assign CLK_2_2024304066 = fenpinqi_2x_CLK_OUT;
  assign CLK_IN_0_1 = CLK_2024304066;
  use_my_ip_fenpinqi_1_0 fenpinqi_10x_2024304066
       (.CLK_IN(CLK_IN_0_1),
        .CLK_OUT(fenpinqi_10x_CLK_OUT));
  use_my_ip_fenpinqi_2_0 fenpinqi_20x_2024304066
       (.CLK_IN(CLK_IN_0_1),
        .CLK_OUT(fenpinqi_20x_CLK_OUT));
  use_my_ip_fenpinqi_0_0 fenpinqi_2x_2024304066
       (.CLK_IN(CLK_IN_0_1),
        .CLK_OUT(fenpinqi_2x_CLK_OUT));
endmodule
